`timescale 1ns / 1ps

module frecuencyDivider(Clock_i,Clock_OneSecond_o,prueba);
 
input Clock_i;
output reg Clock_OneSecond_o=0;
output reg prueba=0;
reg [25:0]counter=26'd0;

 
always @( posedge Clock_i)
	begin	
		if(counter==26'd50000000)begin
				counter<=26'd0;
				Clock_OneSecond_o <= !Clock_OneSecond_o ;
				
				prueba<=!prueba;
				end
		else
				counter <= counter + 1;
				if(counter==0)begin Clock_OneSecond_o <= 0; end
				
				
	end
	
endmodule
